Field of the Invention
This field of the present application relates in general to a method for analysis of processing of a semiconductor wafer and an apparatus for the processing of a semiconductor wafer.
Brief Description of the Related Art
It will be appreciated that the term “semiconductor wafer” as used in this disclosure is intended to imply wafers used in the manufacture of all types of semiconductor devices, including, but not limited to, memory devices, ASICS, logic circuits such as controllers or microprocessors, etc., liquid crystal panels, and photovoltaic devices.
Current trends in the processing of the semiconductor wafers mean that overlay and critical dimension budgets shrink with shrinking ground rules and manufacturing processes are becoming more aggressive. Non-limiting examples of such aggressive manufacturing processes include, but are not limited to, multiple patterning, high aspect ratio etching or deposition of exotic materials on a surface of the semiconductor wafer. The non-uniformity of some manufacturing processes over the semiconductor wafer surface and a plurality of manufacturing process steps may result in non-uniform stress being applied to the semiconductor wafer. When the semiconductor wafer deforms from one manufacturing process step to a subsequent manufacturing process step, e.g. from one lower layer to a subsequent layer on top of the lower layer, patterns in the upper layer may become misaligned to patterns in the lower layer. For the error free functioning of a semiconductor device the relative position of patterns on the different layers to each other is relevant. These relative positional errors are termed “overlay errors”.
A further issue that arises using the aggressive manufacturing processes are the so-called critical dimensions (CDs). This term is used to indicate the dimensions of critical patterns on the surface of the semiconductor wafer. These features are measured after processing, such as the patterning of the lithographic layer, or etching, etc., in order to verify the quality of the exposure and development process.
In practice, there are multiple measurement parameters, which need to be considered when deciding whether microelectronic devices manufactured on the semiconductor wafer are likely to perform according to specifications. The use of the overlay measurements and CD measurements is merely used as an illustration.
FIG. 6A shows an example of the process window used in the manufacture of microelectronic devices on the semiconductor wafers. The process window is shown as an idealised three-dimensional cube in which all (or a majority of) measurements of the processing data for the semiconductor wafers should fall. It should be noted that in practice the measurements are made only in a selection of different fields or areas of the semiconductor wafer and the conclusion is drawn that the semiconductor wafer as a whole is good if the measurements all (or at least a majority) fall within the volume of the box. Measured processing data falling outside of the process window may lead to the semiconductor wafer being considered to be “defective” and the semiconductor wafer may therefore be rejected by a quality controller.
In practice, the boundaries of the process window are likely to be more “fuzzy” and not so clear as the theory and practice has been applied to date. This can be illustrated with respect to the simple feature shown in FIGS. 5A and 5B, which illustrate a non-limiting example of the use of the overlay measurements and critical dimension measurements to determine whether the overlay measurements and the critical dimension measurements are within tolerance limits. FIGS. 5A and 5B show the overlap of a contact L2 with a metallisation line L1. It will be seen that, in FIG. 5A, there is an overlay error of the contact L2 with respect to the metallisation line L1 and a CD error of the contact L2 (i.e. too small). The area of overlap between the contact L2 and the metallisation line L1 is therefore too small to give an adequate electrical connection. On the other hand, in FIG. 5B, the width of the metallisation line L1 is nominally too wide, i.e. the metallisation line L1 has a CD error, and the overlay error for the contact L2 with respect to the metallisation line L1 is identical with that of FIG. 5A, as L2 has in this example no CD error. However, in the example of FIG. 5B, the area of overlap of the contact L2 and the metallisation line L1 is sufficient for a good electrical connection.
FIG. 5B illustrates therefore that there would be no need to reject this particular semiconductor wafer as being defective, even if the overlay measurements and the CD measurements indicate that the manufactured microelectronic device formed on the semiconductor layer is (theoretically) likely to fall outside of the process window. It will be noted that, in this particular simplified example, we have considered only two of the plurality of factors, such as other features and/or parameters, that will affect the performance of the manufacture microelectronic device. The idealised cube of FIG. 6A is, in other words, more like the polyhedron of FIG. 6B in which the various measurements influence each other. It will also be noted that in FIGS. 6A and 6B the process window is shown as a three-dimensional feature for illustrative purposes only and that the process window has, in fact, many more dimensions, i.e. n-dimensions, many of which influence each other.
Gupta et al disclose in the paper “Full chip two-layer DN and overlay process window analysis”, Proc. of SPIE, vol. 9427, 94270H-1 to 94270H-6 an investigation of a two-layer model based analysis of CD and overlay errors. This paper discloses the concept of using measurement data from a first layer to dictate how to process the second layer in order to improve the yield of a semiconductor wafer.
A method for designing a semiconductor chip is known from U.S. Pat. No. 7,941,780 B2 (IBM), which teaches use of a design automation tool to determine an intersect area (or overlap) between a first projected physical area of a first design shape and a second projected physical area of a second design shape. The '780 patent also teaches modifying the first design shape and the second design shape if the determined intersect area is less than a predetermined value.
U.S. Pat. No. 6,892,365 B2 (IBM) teaches a method of predicting overlay failure of circuit configurations on adjacent, lithographically produced layers of a semiconductor wafer by providing design configurations for circuit portions to be lithographically produced on one or more adjacent layer of a semiconductor wafer and predicting shape and alignment for each circuit portions on each adjacent layer using one or more predetermined values for process fluctuation or misalignment error.
These prior art documents all teach the concept of simulating the manufacture of layers on the semiconductor wafer and then making adjustments to the process parameters to try and improve the yield of the semiconductor wafers.